
#ifndef _MMP_REG_ADX2002_H_
#define _MMP_REG_ADX2002_H_
#include "mmp_register.h"

typedef enum
{
	ADX2002_BANDGAP_CTL1 = 0x00,
	ADX2002_BANDGAP_CTL2,
	ADX2002_BANDGAP_CTL3,
	ADX2002_BAT_CTL1,
	ADX2002_BAT_CTL2,
	ADX2002_DCDC_1_CTL1,
	ADX2002_DCDC_1_CTL2,
	ADX2002_DCDC_1_CTL3,
	ADX2002_DCDC_1_CTL4,
	ADX2002_DCDC_1_CTL5,
	ADX2002_DCDC_1_CTL6,
	ADX2002_DCDC_2_CTL1,
	ADX2002_DCDC_2_CTL2,
	ADX2002_DCDC_2_CTL3,
	ADX2002_DCDC_2_CTL4,
	ADX2002_DCDC_2_CTL5,
	ADX2002_DCDC_2_CTL6,
	ADX2002_DCDC_3_CTL1,
	ADX2002_DCDC_3_CTL2,
	ADX2002_DCDC_3_CTL3,
	ADX2002_DCDC_3_CTL4,
	ADX2002_DCDC_3_CTL5,
	ADX2002_DCDC_3_CTL6,
	ADX2002_POWERON_CTL = 0x19,
	ADX2002_RTC_CLK_CTL	= 0x1a,
	ADX2002_I2C_SOFTRESET = 0x1b,
	ADX2002_TP_0 = 0x20,
	ADX2002_TP_1,
	ADX2002_TP_2,
	ADX2002_TP_3,
	ADX2002_TP_4,
	ADX2002_TP_5,
	ADX2002_TP_6,
	ADX2002_TP_7,
	ADX2002_TP_8,
	ADX2002_TP_9,
	ADX2002_RTC_SEC = 0x30,
	ADX2002_RTC_MIN,
	ADX2002_RTC_HOUR,
	ADX2002_RTC_DATE,
	ADX2002_RTC_MON,
	ADX2002_RTC_YEAR,
	ADX2002_RTC_DAY,
	ADX2002_RTC_ALARM1_H,
	ADX2002_RTC_ALARM1_M,
	ADX2002_RTC_ALARM1_DATE,
	ADX2002_RTC_ALARM1_DAY,
	ADX2002_RTC_ALARM2_H,
	ADX2002_RTC_ALARM2_M,
	ADX2002_RTC_ALARM2_DATE,
	ADX2002_RTC_ALARM2_DAY,
	ADX2002_RTC_INT_CTL,
	ADX2002_REG_SRAM = 0x60,
	ADX2002_WDT_CTL	= 0x61,
	ADX2002_CHIP_INT_STATUS = 0x62,
	ADX2002_CHIP_INT_EN = 0x63,
	ADX2002_TP_TM0 = 0x70,
	ADX2002_TP_TM1,
	ADX2002_TP_TM2,
	ADX2002_TP_TM3,
	ADX2002_TP_TM4,
	ADX2002_TP_TM5,
	ADX2002_DCDC1_CTL7 = 0x76,
	ADX2002_DCDC1_CTL8,
	ADX2002_DCDC2_CTL7,
	ADX2002_DCDC2_CTL8,
	ADX2002_DCDC3_CTL7,
	ADX2002_DCDC3_CTL8,
	ADX2002_DC123_CTL,
	ADX2002_REVISON = 0x7D,
	ADX2002_LDO_1_CTL = 0x80,
	ADX2002_LDO_2_CTL,
	ADX2002_LDO_3_CTL,
	ADX2002_LDO_4_CTL,
	ADX2002_LDO_5_CTL,
	ADX2002_LDO_DISCHARGE_EN,
	ADX2002_CURRENT_SET1 = 0x86,
	ADX2002_CURRENT_SET2,
	ADX2002_CURRENT_SET3,
	ADX2002_CLASSG_VOL_CTL1 = 0x90,
	ADX2002_CLASSG_VOL_CTL2,
	ADX2002_CLASSG_PUMP_SET1,
	ADX2002_CLASSG_PUMP_SET2,
	ADX2002_CLASSG_HEAD_SET1,
	ADX2002_CLASSG_HEAD_SET2 
}ADX2002_REG;
#endif