
#ifndef _MMP_REG_ADX2015_H_
#define _MMP_REG_ADX2015_H_

#include "config_fw.h"

#if (ADX2015_EN)

#include "mmp_register.h"

#define ADX2015_I_Limit_INC_500mA	0x03
#define ADX2015_I_Limit_INC_300mA	0x02
#define ADX2015_I_Limit_INC_100mA	0x01
#define ADX2015_I_Limit_DEFAULT		0x00

#define ADX2015_I_Charge_90mA		0x07
#define ADX2015_I_Charge_180mA		0x06
#define ADX2015_I_Charge_270mA		0x05
#define ADX2015_I_Charge_360mA		0x04
#define ADX2015_I_Charge_450mA		0x03
#define ADX2015_I_Charge_540mA		0x02
#define ADX2015_I_Charge_630mA		0x01
#define ADX2015_I_Charge_720mA		0x00

typedef enum
{
	ADX2015_BANDGAP_CTL1 = 0x00,
	ADX2015_BANDGAP_CTL2,
	ADX2015_BANDGAP_CTL3,
	ADX2015_VDD_CTRL,
	ADX2015_PWR_ONOFF_SEQ_CTRL,
	ADX2015_DCDC_1_CTL1,	//0x05
	ADX2015_DCDC_1_CTL2,
	ADX2015_DCDC_1_CTL3,
	ADX2015_DCDC_1_CTL4,
	ADX2015_DCDC_1_CTL5,
	ADX2015_DCDC_1_CTL6,	//0x0a
	ADX2015_DCDC_2_CTL1,
	ADX2015_DCDC_2_CTL2,
	ADX2015_DCDC_2_CTL3,
	ADX2015_DCDC_2_CTL4,
	ADX2015_DCDC_2_CTL5,	//0x0f
	ADX2015_DCDC_2_CTL6,	//0x10
	ADX2015_DCDC_3_CTL1,
	ADX2015_DCDC_3_CTL2,
	ADX2015_DCDC_3_CTL3,
	ADX2015_DCDC_3_CTL4,
	ADX2015_DCDC_3_CTL5,	
	ADX2015_DCDC_3_CTL6,
	ADX2015_POWERON_CTL = 0x19,
	ADX2015_RTC_CLK_CTL	= 0x1a,
	ADX2015_I2C_SOFTRESET = 0x1b,
	ADX2015_POWER_ON_STATUS,
	ADX2015_TP_0 = 0x20,
	ADX2015_TP_1,
	ADX2015_TP_2,
	ADX2015_TP_3,
	ADX2015_TP_4,
	ADX2015_TP_5,
	ADX2015_TP_6,
	ADX2015_TP_7,
	ADX2015_TP_8,
	ADX2015_TP_9,
	ADX2015_RTC_SEC = 0x30,
	ADX2015_RTC_MIN,
	ADX2015_RTC_HOUR,
	ADX2015_RTC_DATE,
	ADX2015_RTC_MON,
	ADX2015_RTC_YEAR,
	ADX2015_RTC_DAY,
	ADX2015_RTC_ALARM1_H,	//0x37
	ADX2015_RTC_ALARM1_M,	//0x38
	ADX2015_RTC_ALARM1_DATE,	//0x39
	ADX2015_RTC_ALARM1_DAY,	//0x3a
	ADX2015_RTC_ALARM2_H,	
	ADX2015_RTC_ALARM2_M,
	ADX2015_RTC_ALARM2_DATE,
	ADX2015_RTC_ALARM2_DAY,
	ADX2015_RTC_INT_CTL,		//0x3f
	ADX2015_REG_SRAM = 0x60,
	ADX2015_WDT_CTL	= 0x61,
	ADX2015_CHIP_INTA_STATUS = 0x62,
	ADX2015_CHIP_INTA_EN = 0x63,
	ADX2015_CHIP_INTB_STATUS = 0x64,
	ADX2015_CHIP_INTB_EN = 0x65,
	ADX2015_TP_TM0 = 0x70,
	ADX2015_TP_TM1,
	ADX2015_TP_TM2,
	ADX2015_TP_TM3,
	ADX2015_TP_TM4,
	ADX2015_TP_TM5,
	ADX2015_LDO_1_CTL = 0x80,
	ADX2015_LDO_2_CTL,
	ADX2015_LDO_3_CTL,
	ADX2015_CP_CTL,
	ADX2015_LDO_DISCHARGE_EN = 0x85,
	ADX2015_CURRENT_SET1 = 0x86,
	ADX2015_CURRENT_SET2,
	ADX2015_CURRENT_SET3,
	ADX2015_CLASSG_VOL_CTL1 = 0x90,
	ADX2015_CLASSG_VOL_CTL2,
	ADX2015_CLASSG_PUMP_SET1,
	ADX2015_CLASSG_PUMP_SET2,
	ADX2015_CLASSG_HEAD_SET1,
	ADX2015_CLASSG_HEAD_SET2,
	ADX2015_BATCHR_BCCR1 = 0x98,
	ADX2015_BATCHR_BCCR2,
	ADX2015_BATCHR_BCCR3,
	ADX2015_BATCHR_BCCR4,
	ADX2015_BATCHR_BCCR5,
	ADX2015_BATCHR_BCCR6,
	ADX2015_BATCHR_BCCR7,
	ADX2015_OTP_CTRL1 = 0xA4,
	ADX2015_OTP_ACCESS_ADDR = 0xA6,
	ADX2015_OTP_WRITE_DATA,
	ADX2015_OTP_READ_DATA,
	ADX2015_CHG_CTL1 = 0xA9,
	ADX2015_CHG_CTL2 = 0xAA,
	ADX2015_PPM_CTL1 = 0xAB,
	ADX2015_PPM_CTL2,
	ADX2015_PPM_CTL3,
	ADX2015_PPM_CTL4,
	ADX2015_IR_CLR = 0xC0,
	ADX2015_IR_DATA0,
	ADX2015_IR_DATA1,
	ADX2015_IR_DATA2,
	ADX2015_IR_DATA3,
	ADX2015_IR_CTRL,
	ADX2015_IR_PWR_CODE,
	ADX2015_OTHER
}ADX2015_REG;

typedef enum _ADX2015_ADC_TYPE
{
	ADX2015_ADC_AUX1 = 0,
	ADX2015_ADC_AUX2	,
	ADX2015_ADC_AUX3	,
	ADX2015_ADC_AUX4	,
	ADX2015_ADC_WIPER	, // Equal to AUX3
	ADX2015_ADC_TP_PRE	,
	ADX2015_ADC_X_CO	,
	ADX2015_ADC_Y_CO	,
	ADX2015_ADC_MAX	
}ADX2015_ADC_TYPE;

#endif      // #if (ADX2015_EN)

#endif      // #ifndef _MMP_REG_ADX2015_H_
